1. Field of the Invention
The present invention relates to a semiconductor packaging substrate, especially, to a semiconductor packaging substrate with enhanced protection against electrostatic discharge.
2. Description of the Related Art
Electrostatic charges are commonly created by the contact and separation of two materials. Virtually all materials, even conductor, can be triboelectrically charged and the voltage of the electrostatic charges, can be very high, even up to thousands of volts. Therefore, if the electrostatic charges are suddenly discharged, the electronic components may be seriously damaged, which is so-called electrostatic discharge (ESD). ESD is likely to occur throughout the semiconductor packaging process leading to unexpected damage to the integrated circuit, IC. 
As shown in FIG. 1, a conventional semiconductor packaging substrate 100 primarily comprises a dielectric layer 110, a plurality of leads 120 and a solder mask (not shown in the figure), where a plurality of packaging units 111 are defined on the dielectric layer 110. The leads 120 are formed in the packaging units 111 and are partially covered by the solder mask. A plurality of equal-spacing sprocket holes and the plating buses 150 are disposed on the peripheral areas of the two longitudinal sides of the substrate 100. A plurality of guide lines 130 are formed between the packaging units 111 and are electrically connected to some of the leads 120, such as ground leads, to provide an electrostatic dissipation path, where the two ends of the guide lines 130 are electrically connected to the plating buses 150 at the two longitudinal sides of the substrate 100. However, the guide lines 130 are thin long traces and in connection to the plating buses 150 provides only an electrostatic dissipation path of direct grounding. Ionizers in this case can hardly provide any effect on electrostatic dissipation. Therefore, throughout the packaging process, the accumulated electrostatic charges can be rapidly dissipated only when the plating buses 150 are grounded. If the plating buses 150 are not grounded, the ESD sensitive leads may be damaged by the sudden electrostatic discharge leading to electrical failure of the chip.
In R.O.C. Taiwan Patent No. I228819, entitled “Semiconductor packaging structure”, a semiconductor packaging substrate similar to the one mentioned above is revealed. A conductive trace directly connects a ground lead to a guard ring for electrostatic dissipation. However, since electrostatic discharge usually occurs suddenly and the guard ring which is thin and long in shape only provides a small dissipation area, the design is unlikely to render enough protection to the leads from thousands of volts of ESD.
In Taiwan Patent No. I227939, entitled “Encapsulated structure of COF (chip on film)”, a semiconductor package is revealed. A structure of embedded capacitor is fabricated in the gap between the chip and the substrate, where the embedded capacitor is composed of two metal plates, one disposed on the chip and the other on the substrate, opposite to and separated from each other. However, this design not only will alter the package structure but increase the manufacturing cost to fabricate the embedded capacitor in between the chip and the substrate. The embedded capacitor may also cause some negative impacts on the reliability of the package structures since the integrity of the package structure has been disturbed by inserting the embedded capacitor in-between the chip and the substrate and its capacitance is not stable due to the shift of the chip. Moreover, since the embedded capacitor is disposed in the gap between the chip and the substrate, the electrostatic charges are prone to accumulate within the tiny space and can hardly be removed; the effectiveness of electrostatic dissipation is hence reduced.